Memory bandwidth continues to be a limitation on the ability of high speed CPU processors to make effective use of their processing capabilities. CPU designers have developed cache memory to reduce the average time to access data from the main memory. A cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels (L1, L2, L3, etc.). Various techniques such as larger L1 and L2 caches have limitations as the cost of the silicon and the operating power of the Static RAM (SRAM) memory are limiting their use. Recent approaches have been to add a Level 3 to help with getting data from system memory to multiple processor cores. Intel® has recently added a level 4 (L4) on package cache by using embedded DRAM (Dynamic RAM) that is shared between the multiprocessor cores and the on-die graphics processor and also used as a victim cache for the CPU's L3 cache.
Recognizing years of fading processor speed improvement due to conventional memory limitations and the futility of adding more levels of cache, significant R&D is currently directed to designing and manufacturing nanoscale memory devices. These devices offer the potential to replace ail cache levels as well as the system DRAM memory and potentiality the storage memory often implemented in flash, optical, or magnetic technologies. These nanoscale memory devices are typically implemented in cross-bar arrays allowing for very dense, low cost, and low power memory systems that offer to not only dramatically increase the processing speeds by orders of magnitude, but also lower cost. These improvements come in addition to decreasing power consumption for the next generation of computing devices without having to rely on the lithographic shrinking of transistors. However, to make this future vision possible, various technological issues need to be addressed to continually improve the performance of devices which have been presently fabricated.